In sub-micron Complimentary Metal-Oxide Semiconductor (CMOS) manufacturing, self-aligned contact (SAC) technology has been successfully used to achieve chip size reduction. In conventional SAC processes gate film stacks are formed over the substrate, and spacers are formed on opposite sides of each gate film stack. An etch stop layer (e.g., silicon nitride) and a pre-metal dielectric layer are then deposited so as to cover the gate film stacks. An etch is performed to form contact openings that extend through the pre-metal dielectric layer. This etch stops on the etch stop layer. The exposed portions of the etch stop layer are then removed, exposing the structure that is to be contacted. A metal layer is then deposited and planarized to complete the self-aligned contact. The etch stop layer prevents over-etch, aligning the contact with the structure to be contacted and preventing current leakage that could result from improper alignment.
Side surfaces of conventional gate film stacks are nearly vertical, producing high-aspect ratio openings that must be filled by pre-metal dielectric. When pre-metal dielectric is deposited into these vertical or nearly vertical, high aspect ration openings, voids can form in the dielectric. These voids in the pre-metal dielectric layer can lead to bridging defects. More particularly, when the self-aligned contact etch opens up a void, metal can fill the void, causing undesired electrical contact between adjoining contacts and structures, causing current leakage. This results in reduced yield and increased manufacturing cost.
Accordingly there is a need for a process for forming a void-free dielectric film. Also, there is a need for CMOS devices that do not have bridging defects. The present invention meets the above needs.